Semiconductor memory devices are generally divided into volatile semiconductor memory devices, such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices, and nonvolatile semiconductor memory devices, such as erasable programmable read only memory (EPROM) devices, electrically erasable programmable read only memory (EEPROM) devices and flash memory devices. Volatile semiconductor memory devices may lose data stored therein when power is turned off, whereas nonvolatile semiconductor memory devices can maintain data stored therein after power is turned off.
In contrast, ferroelectric random access memory (FRAM) devices may have volatile characteristics of a RAM device and also nonvolatile characteristics of a ROM device. Currently, the operating speed of FRAM devices may be less than that of DRAM devices due to less advanced techniques for manufacturing FRAM devices. However, FRAM devices may have high data retention capabilities that can maintain data stored therein after power is off due at least in part to a ferroelectric layer with a spontaneous polarization characteristic. Accordingly, FRAM devices may be more suitable for use in an operating unit that does not require a rapid input/output of information, or in a memory device, that maintains stored information. Additionally, the FRAM device may be operated at a voltage lower than that of the EPROM device or the EEPROM device, and data stored in the FRAM device may be maintained for a longer storage time.
Ferroelectric materials such as PZT [Pb(Zr, Ti)O3] and/or SBT (SrBi2Ta2O9) may be used in FRAM devices. A ferroelectric layer of PZT may be formed at a relatively low temperature of below about 650° C. Additionally, the ferroelectric layer of PZT may have a relatively large polarization. However, the ferroelectric layer of PZT generally may have relatively poor fatigue characteristics and also may include harmful ingredients, such as lead (Pb). A ferroelectric layer of SBT may have improved fatigue characteristics and also may have a polarization-voltage (P-V) hysteresis that does not imprint in a specific direction. However, the ferroelectric layer of SBT may be formed through a thermal treatment at a relatively high temperature of above about 800° C.
Conventional methods of manufacturing FRAM devices including ferroelectric layers are disclosed in Korean Laid-Open Patent Publication No. 2001-113271, Korean Laid-Open Patent Publication No. 2001-4306, U.S. Pat. No. 6,351,006 issued to Yamakawa et al., and U.S. Pat. No. 6,194,228 issued to Fujiki et al.
When a ferroelectric layer including PZT is formed on a substrate by a metal organic chemical vapor deposition (MOCVD) process, the ferroelectric layer may have a rough surface such that the FRAM device including the rough ferroelectric layer may have relatively poor electrical and/or ferroelectric characteristics. In particular, an upper electrode may not be firmly attached to the rough ferroelectric layer, and as such, the upper electrode may be easily detached from the rough ferroelectric layer. Additionally, charges may be irregularly distributed on the rough surface of the ferroelectric layer which may thereby deteriorate the electrical characteristics of the FRAM device.
Korean Laid-Open Patent Publication No. 2004-34172 discloses a method of stabilizing a layer using tantalum oxide while providing a nitrogen gas. In this method, a formation process of the layer includes a stabilization process, a deposition process and a purging process. The stabilization process may be performed under an oxygen atmosphere, the deposition process may be performed under an inactive atmosphere, and the purging process may be performed under oxygen or nitrogen atmosphere. When the tantalum oxide layer is deposited, an inactive gas (such as a nitrogen gas without an oxygen gas) may be provided to reduce and/or prevent the formation of oxygen atoms on the lower electrode for depositing the tantalum oxide.
Additionally, to reduce and/or prevent the formation of byproducts between an upper electrode and a capping layer when the capping layer is formed on the upper electrode, Korean Laid-Open Patent Publication No. 2003-78394 discloses a method of stabilizing under a nitrogen atmosphere, and then purging the nitrogen gas. In the above method, after a capacitor including a lower electrode, a dielectric layer and an upper electrode is formed, the purging process may be performed to form a capping layer. In the stabilization process and/or the purging process, a nitrogen gas may be used to reduce and/or prevent an oxygen gas for forming the capping layer from diffusing to the upper electrode.